Allen Bradley ICS

Overview

Brand Name:	ICS TRIPLEX
Model Number:	T8110B
Country of Origin:	USA
Packaging Details:	Original new Factory Sealed
Delivery Time:	Delivery time in stock
Payment Terms:	T/T

Contact for quotation

Sales Manager:	Stella
Send an email:	[email protected]
Contact in Whatsapp:	+86 18159889985

Specifications

Specification	Details
Module Type	Trusted TMR Processor Module
Architecture	Triple Modular Redundancy (TMR), 3-2-0 fault tolerant, Hardware Implemented Fault Tolerant (HIFT) lock-step configuration
Processor	Three Motorola Power PC series processors (one per fault containment region)
Processor Clock Speed	100 MHz
Safety Integrity Level	TÜV Certified IEC 61508 SIL 3
Memory	DRAM: 16 MB EDO 60 ns; EPROM: 512 kB; FLASH: 2 MB; NVRAM: 128 kB
Retained Variable Storage	Boolean: 1 byte; Analog: 4 bytes; Timer: 5 bytes
Serial Communication Ports	1 × RS232 (front panel diagnostics); 2 × RS422/485 configurable 2/4-wire; 1 × RS485 2-wire (all exclusive to T8110B)
Time Synchronization	IRIG-B002 and IRIG-B122 (exclusive to T8110B)
Operating Temperature	0 °C to +60 °C (32 °F to 140 °F)
Storage / Transport Temperature	–25 °C to +70 °C (–13 °F to 158 °F)
Relative Humidity	10 % – 95 %, non-condensing
Power Supply Voltage	20 Vdc to 32 Vdc
Maximum Load / Heat Dissipation	80 W
Dimensions (H × W × D)	266 mm × 93 mm × 303 mm (10.5 in × 3.6 in × 12.0 in)
Weight	2.94 kg (6.48 lb)
Compatible Chassis	T8100
I/O Interface	Triple redundant Inter-Module Bus
SOE Buffer	1000 events (transferred to CI buffer of 4000 events)
Certifications	TÜV IEC 61508 SIL 3, ATEX, IECEx, UL Class I Div 2

Description

The ICS TRIPLEX T8110B is a Trusted TMR processor module built around a Triple Modular Redundant (TMR) lock‑step architecture with three independent fault containment regions. Designed for IEC 61508 SIL 3 safety instrumented functions, the T8110B executes each application on all three processors simultaneously, voting results via a 2‑out‑of‑3 mechanism to mask single faults. The module adds IRIG‑B time synchronisation, two additional serial ports and dedicated fault/fail relays. As the central logic solver of a Trusted system, the ICS TRIPLEX T8110B delivers non‑stop operation, comprehensive online diagnostics and hot‑swap support, making it the core of high‑integrity safety controllers for emergency shutdown, fire & gas and turbine control applications .

Applications

Emergency Shutdown (ESD) Systems – executes high‑integrity trip logic for pressure, temperature and flow monitoring in refineries, LNG plants and chemical reactors

Fire & Gas (F&G) Detection – coordinates flame detectors, gas sensors and manual call points to initiate ventilation or suppression

Burner Management Systems (BMS) – controls boiler and furnace ignition sequences, flame monitoring and purge cycles for SIL‑3 rated combustion safety

Turbine Control – provides overspeed protection, vibration monitoring and emergency stop logic for gas and steam turbines in power generation

Critical Process Control – acts as the central safety controller for high‑risk batch and continuous processes in oil & gas, petrochemical and pharmaceutical industries

High Availability Safety Instrumented Systems (SIS) – functions as the main processor within a redundant Trusted chassis, supporting companion slot configuration for bumpless changeover during maintenance

Features

Triple Modular Redundancy (TMR) with 3‑2‑0 fault tolerance – three processors run synchronously; after a single fault the system continues as 2‑out‑of‑3, and after two faults it shuts down safely

Hardware Implemented Fault Tolerant (HIFT) architecture – automatic fault detection and isolation at the hardware level; no external watchdog required

IEC 61508 SIL 3 certified – TÜV‑approved for safety instrumented functions up to the highest integrity level

Hot‑swap capability – online module replacement without program reload when used in companion slot configuration

Comprehensive online diagnostics – periodic self‑tests of processors, memory, clocks and buses; faults stored in time‑stamped historian

IRIG‑B time synchronisation – IRIG‑B002 and IRIG‑B122 inputs for 1 ms SOE timestamping across distributed systems (exclusive to T8110B)

Multiple serial communication ports – front panel RS232 diagnostics port plus dedicated RS422/485 ports for MODBUS slave connectivity (exclusive to T8110B)

Full IEC 61131‑3 programming language support – Ladder Diagram, Function Block Diagram, Structured Text, Instruction List and Sequential Function Chart

Dual redundant 24 Vdc power inputs – accepts 20–32 Vdc with automatic failover between two power feeds

Fault / Fail relay outputs – normally‑closed contacts for external annunciation of system faults or shutdown conditions

Functions

Lock‑step application execution – all three processors execute the user program synchronously; each scan cycle includes reading inputs, solving logic and writing outputs

2‑out‑of‑3 (2oo3) voting – input data from the Inter‑Module Bus is voted by each processor; output data from the three processors is voted before transmission

Discrepancy detection – configurable tolerances for analogue voltage (ana_discrep_val), digital input (dig_discrep_val) and output channels (do_discrep_val); discrepancies trigger fault alarms after a user‑defined interval

Active / Standby processor negotiation – when a second T8110B is installed in a companion slot, the active processor educates the standby and coordinates bumpless changeover if the active module is removed or fails

Sequence of Events (SOE) logging – captures timestamped state changes of all inputs with 1 ms resolution; logs are stored in NVRAM and can be uploaded to an engineering workstation

Real‑time clock (RTC) management – maintains date/time for SOE entries and retains the clock during power loss via NVRAM; can be read/written from the application program via dedicated RTC racks (TTMRP_3, TTMRP_4, TTMRP_5)

System.INI configuration – all operating parameters (poll intervals, discrepancy thresholds, chassis counts, IRIG‑B mode) are defined in a single text file downloaded via the Toolset

Fault reset – clears latched faults and restarts diagnostics; can be triggered by the front panel pushbutton or remotely via the engineering workstation

Maintenance enable keyswitch – two‑position switch (Run / Maintain) on the front panel locks the memory against unauthorised downloads; removable key prevents physical tampering

FAQ

Q1: What safety integrity level (SIL) does the T8110B support?
A1: The T8110B is TÜV certified for IEC 61508 SIL 3 when used as the main processor within a Trusted TMR system. The 2oo3 voting architecture ensures SIL 3 integrity even after a single component fault.

Q2: Can the T8110B be replaced while the system remains powered?
A2: Yes. When a second T8110B is installed in the companion slot, the module supports hot‑swap replacement. The standby processor takes over before the active module is removed, preventing any interruption to the control function.

Q3: What time synchronisation options are available on the T8110B?
A3: The T8110B accepts both IRIG‑B002 (RS485/422 differential) and IRIG‑B122 (1 kHz amplitude modulated) input signals. These enable sub‑millisecond timestamping of SOE events across distributed Trusted chassis.

Q4: How do I configure discrepancy thresholds for input modules?
A4: Use the System.INI file. For T8403C digital inputs, set dig_discrep_val (default 250 / 512 V ≈ 512 mV). For T8431C analogue inputs, set ana_discrep_val (default 40 / 512 V ≈ 78 mV). The processor applies these to all matching I/O modules.

Q5: What happens if two processor slices fail in a dual T8110B configuration?
A5: The active T8110B can tolerate one slice failure (degrading from TMR to dual operation). If a second slice in the same module fails, that processor module automatically isolates itself; the standby T8110B remains operational, maintaining system integrity without shutdown.

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